With reference to FIG. 1 there is shown a representation of part of a computer system comprising an initiator 102 and a memory 104 which are connected via a bus 106. The initiator 102 may be any component in the system capable of writing data to the memory, such as a write engine. The initiator 102 sends a write request for writing data to the memory 104 over the bus 106. The write request is received at the memory 104 and the data is written into the memory 104.
Ensuring the security and integrity of the data transmitted over the bus 106 may be a problem. The data in the write request may be corrupted in transit on the bus 106 or may be corrupted as it is written into the memory 104. The corruption of the data may be due to a poor-quality communication channel on the bus 106. Alternatively, the corruption of the data may be due to deliberate interference, such as power glitching or clock glitching. Power glitching is where the power supply in the system is affected such that data being written to the memory 104 is corrupted during the write operation. Clock glitching is where the clock signals are affected such that data being written to the memory 104 is corrupted during the write operation.
There is therefore required a method for ensuring that data is written to the memory 104 without being corrupted. In other words, there is required a method for ensuring that the data written to the memory 104 is the same as the data that was sent from the initiator 102. One method for achieving this uses error detection bits representing an error detection value, such as parity bits or some other Error Checking and Correcting (ECC) bits. The data is used to generate the error detection bits before the data is sent to the memory 104. The error detection bits correspond to the data before the data is sent to the memory 104. If the data has been modified since the error detection bits were generated, then the error detection bits will no longer correspond to the modified data. This allows the error detection bits to be used to check whether the data has been modified since the error detection bits were generated. The error detection bits are sent with the data over the bus 106 to the memory, such that the memory 104 can check that the error detection bits and the data received on the bus 106 correspond to each other.
One method for sending error detection bits with the data is to expand the number of signals on the bus to include the extra error detection bits. However, this method has some significant problems. Firstly, the expanded bus specification requires larger and more complex bus logic. Secondly, the specification of the devices using the extra error detection bits on the bus will need to be modified in order to correctly handle the extra bits.
Part of the memory's address map may be allocated for storing the error detection bits. However, this reduces the memory capacity available for the data, since some of the memory space is allocated for storing error detection bits. Furthermore, the initiator needs to be aware of the allocated location in the memory in order to send the error detection bits to the correct part of the memory. This requires the initiator to have a sufficient level of intelligence to send the error detection bits to the required memory address.
There is therefore required a method for ensuring that data is written to the memory 104 without being corrupted, which overcomes the problems in the prior art described above.